AMD EPYC 9006 Venice: 256 cores, 16 memory channels and the MRDIMM question

AMD announced general availability of the EPYC 9006 processors, codename Venice, as SP7 processors on November 10, 2026, the first server CPUs on Zen 6, built on TSMC's 2-nm process. The platform brings 16 memory channels per socket (RDIMM up to 8000 MT/s or MRDIMM up to 12800 MT/s), up to 8 TB of memory and PCIe 6.0. The top model 9996 puts 256 cores and 600 watts of TDP on the datasheet, at 14,904 dollars in the 1,000-unit list. Two testers, Phoronix and Level1Techs, published their own measurements the same day. We own no Venice hardware; every figure here comes from the named sources, with the test vehicle and test date attached.

AMD makes the EPYC processors and is the source of the prices, clock rates and comparison values cited in this post. We re-measured none of it; independent figures come from Phoronix and Level1Techs. (Quelle: Simple Icons, file amd.svg (CC0))

What AMD says at launch

The announcement from the AMD newsroom reports availability and sets Intel Xeon systems against Nvidia's Vera and an Arm CPU, the last two as AMD estimates. The Turin comparison values, double the integer throughput, 2.4 times the floating-point rate, 2.7 times the memory bandwidth, 1.4 times HPC and 1.3 times the matrix operations, come from AMD's briefings; Phoronix relayed them on measurement day. These are vendor figures against AMD's own baseline, not re-measured by us. The press kit bundles images and launch-day announcements, among them the embedded variant.

Ratio figures from AMD's briefings, relayed by Phoronix on measurement day; 200 percent means double the predecessor. (Quelle: Phoronix (AMD briefing), Nov 10, 2026)

Model	Cores/threads	Clock base/boost	L3 cache	TDP	Price from 1,000 units
EPYC 9996	256 / 512	2.55 / 4.1 GHz	1,024 MB	600 W (cTDP 400–600)	14,904 USD
EPYC 9686F	96 / 192	4.05 / 5.3 GHz (launch: 5.0, see below)	384 MB	600 W default	11,434 USD

Table 1: two launch models; the 9996 per the launch announcement of November 10, 2026, the 9686F per the current AMD datasheet, accessed November 11, 2026; prices from the 1,000-unit list.

The socket choice decides the PCIe side: the SP7 carries 96 PCIe 6.0 lanes per socket. The smaller SP8 follows, per AMD, in the first half of 2027; its lane and channel counts remain open in the sources surveyed here.

The bandwidth number and what it costs

AMD advertises "up to 1.6 TB/s" of memory bandwidth per socket. That figure holds with MRDIMM-12800 across all 16 channels and is a theoretical peak. The 9686F datasheet lists 1,024 GB/s with RDIMM-8000 and 1,638 GB/s with MRDIMM-12800 for the two memory sides, each per socket across 16 channels. MRDIMM is no requirement.

Theoretical peak values on full population across 16 channels; Level1Techs measured 1.2 TB/s in a dual system. (Quelle: AMD datasheet, EPYC 9686F, accessed Nov 11, 2026)

Street prices for the MRDIMM modules went unmentioned in every source surveyed here on launch day. AMD's white paper on memory tiering, MEXT inverts the memory math: cold pages move out to NVMe, predicted ones come back before the application asks. Measured with a signoff workload from chip design, Synopsys PrimeTime: against 1.5 TB of full DRAM, half the population with 768 GB plus flash reached about 87 percent of the performance, arithmetically 1.74 times the performance per DRAM dollar. The test vehicle of this AMD-internal measurement from October 2025 was the predecessor EPYC 9755, not Venice; an independent re-measurement does not exist either.

What Phoronix measured independently

Phoronix tested on November 10, 2026 on an air-cooled 2U reference server supplied by AMD, on Ubuntu 26.10 and kernel 7.3, across several hundred individual runs. The figures below come from a dual system with two EPYC 9996, plus the 9686F separately.

In the test suite's geometric mean, the 9996 dual system reaches 1.58 times the output of the predecessor dual system with 9965. A factor of 1.33 of that is the core count, the rest the architecture. In HPC tests Phoronix sees the system at roughly double the output of a dual Xeon 6980P and at the top on performance per watt, despite the 600-watt TDP.

The 9686F, 96 cores with a high clock: at launch Phoronix named 3.4 GHz base, a 5.0 GHz boost and 500 watts default (cTDP 400 to 600), then confirmed 5.3 GHz in production; AMD's current product page lists 4.05 GHz base, 600 watts default and 11,434 dollars. The high-clocked variant also beats Nvidia's new Vera CPU, which Tom's Hardware confirms from its own tests, run over several weeks; their 9996 dual system sat 93 percent above the 9965 dual system in the SPEC CPU 2026 integer rate.

A second measurement rig: Level1Techs

Level1Techs tested two SP7 systems on publication day. On the sourcing: Tom's Hardware contributed its own tests that day, run over several weeks – the NUMA and inference numbers below come solely from Level1Techs; here one party measures.

Measurement test by Level1Techs of November 10, 2026; the NUMA, latency and inference figures below come from this video.

Memory bandwidth: on the ramp to all 16 channels, Level1Techs measured 667 GB/s; on the dual system the team rates AMD's 1.6 TB/s figure too high and calls a good 1.2 TB/s realistic.
NUMA mode: NPS1 sat 9.2 percent behind NPS2 in an inference test and still around five after the kernel warmed up; on SQLite, NPS1 cost 17 percent. Level1Techs recommends NPS2 clearly.
Pointer-chase latency: crossing the socket boundary costs around 50 nanoseconds, one socket sits at roughly 200 nanoseconds. Against Zen 5 the team highlighted the clear uplift in bandwidth per core.
CPU inference with Gemma 3 12B: 36 tokens per second of decode on 96 threads of one socket, 16 on all 192 threads of both sockets; prompt processing managed around 600 tokens per second at best. When generating, the output stays the bottleneck.

Contradictions in the coverage

Three points to sort out, the first already resolved:

The boost clock of the 9686F: AMD's datasheet named 5.0 GHz at launch, Phoronix measured 5.3 GHz in production. The current datasheet itself now carries the 5.3; the 5.0 keeps circulating in older summaries.
The roadmap after SP7: AMD names the SP8 for the first half of 2027, the Level1Techs video the same date. The 3D-cache line 9006X and the low-power line 9006LP "Verano" follow in the second half of 2027, per Phoronix.
Availability: AMD reports OEM systems shipping; Azure stands as a preview, OCI is announced. Level1Techs reports retail at best in late 2027, more likely 2028. Resolution: OEM systems today, cloud instances in stages, broad retail later.

One rule of thumb from the AMD slide deck in the video, that roughly ten Ice Lake and Cascade Lake sockets can be replaced by one, I find in no written AMD source; it stays an oral claim. AMD asserted a similar ratio of 5:1 for Skylake against Genoa in 2022.

What we take from it for our own servers

We have no Venice server; no existing machine in our estate changes with this generation. Two rules I am adding to the checklist anyway; both are measurable before the purchase.

The first is channel population. Whether all 16 channels are filled decides the bandwidth, which Level1Techs saw ramp to 667 GB/s per socket; the pattern hits small platforms too: one of our EPYC boxes, an 8-core CPU, has two modules in six slots. At the next server purchase we check the module population in the datasheet, right next to the capacity figure.

The second is the NUMA mode. Up to 17 percent performance difference depending on the NPS setting, measured by Level1Techs, is more than any tuning round afterwards delivers. Test NPS2 before the rollout, databases first, they react most sensitively.

For language models in your own building the server CPU stays a niche: Level1Techs shows that even a 96-core high-clock processor hits the same wall when generating as small ones do, while our GPU lane with LiteLLM and vLLM plays in different orders of magnitude. We keep watching Venice: MRDIMM prices, the SP8 in the first half of 2027 and the 3D-cache variant in 2027 are the next occasions. More on the topic servers and network; anyone wanting their inference sizing calculated will find the service at Corporate LLM.